An electronic package typically comprises an electronic package substrate, a chip that is mechanically and electrically connected to the electronic package substrate, and encapsulating material that covers and protects the chip and the electrical connections between the chip and the electronic package substrate from mechanical and environmental damage. The primary function of an electronic package substrate is to provide an electrical bridge from a very dense set of electrical terminals or pads on a chip to a corresponding set of electrical terminals or pads on the electronic package substrate, effectively fanning out the electrical connections from the chip so that the chip can be mechanically and electrically connected to the next level of integration such as a printed circuit board (PC board or PCB). Since many chips produces a significant amount of heat during operation, the electronic package also must dissipate the heat and prevent the chip from overheating and becoming unreliable.
There are two principal types of electronic packages commonly in use, each of which is differentiated by the way that a chip is connected to its corresponding electronic package substrate: electronic packages for wire bonded chips (wire bonded electronic packages) and electronic packages for flip chips (flip chip electronic packages). In wire bonded electronic packages, the chip is connected to the corresponding electronic package substrate by tiny wires in a process called wire bonding or by tabs in a process called tab bonding. In flip chip electronic packages, the chip is connected to the corresponding electronic package substrate by small, typically globular conductive connectors, typically tiny spheres of solder called solder bumps. Because both types of electronic packages have the same purpose and function—to provide a bridge between the very dense set of electrical terminals or connectors on a chip to a less dense set of terminals or connectors on a mother board, application board or other PC board—both types of electronic packages share some of the same limitations and problems. Some of these limitations and problems can be addressed by common or similar improvements. However, because the two types of electronic packages have differences in their respective structures and the way that chips are attached to their respective electronic package substrates, there often are differences in the way that certain limitations and problems can be overcome.
To facilitate the design and manufacture of electronic products, industries have adopted various standards for sizes, shapes, and interfaces for connecting electronic packages to PC boards or other circuits. A very common interface for mechanically and electrically connecting an electronic package to a PC board is a ball grid array (BGA). A ball grid array is an array of solder balls (or similar connector/conductors). A BGA electronic package has an array of solder balls (or similar connector/conductors) connected to a corresponding set of solder ball pads on the outside of the electronic package. The solder balls typically are attached to pads on the electronic package in the electronic package assembly process. When an electronic package is attached to a PC board the array of solder balls on the electronic package is aligned with a corresponding set of solder ball pads or connectors on the PC board. The solder balls are melted and fused to the set of solder ball pads on the PC board.
The components of electronic packages are manufactured in very separate and distinct operations and generally by separate firms that specialize in manufacturing such components. Typically, chips are manufactured in substantial quantities by chip manufacturers in what are often called chip foundries. Typically, electronic package substrates are manufactured in substantial quantities in separate operations by firms that specialize in making such substrates. Electronic package substrates are manufactured in various standard sizes defined by industry standards. In yet another separate operation, generally called the electronic package assembly process, chips are bonded to electronic package substrates, and electrical connections are made between the chips and the electronic package substrates.
In wire bonded electronic package assembly process the chip is mechanically bonded to the electronic package substrate using an adhesive paste between the chip and the electronic package substrate. The chip is then electrically connected to the electronic package substrate, by any of several different methods, the most common being wire bonding, but tab bonding has been and still may be used. Wires (or tabs) are connected between pads or terminals on the chip—typically along the periphery of the chip—and pads or terminals on the electronic package substrate—typically along the edge or periphery of the electronic package substrate closest to the chip. After the chip is electrically connected to the electronic package substrate, the chip and the electrical connections are encapsulated or molded with an organic material to protect the chip and its connections from mechanical and environmental damage. As a final step in the assembly process for making BGA electronic packages, solder balls are attached to the electrical pads on the electronic package substrate so that the electronic package ultimately can be connected to a circuit board or more generally to the next level of integration.
With the historic progress in the design and development of chips and chip-making equipment, the size of circuit elements within a chip has decreased, the number of these circuit elements within a chip has increased, the number of electrical connections needed to connect a chip to its corresponding electronic package substrate has increased, and the space for making these connections has decreased. Instead of utilizing only the area along the periphery of a chip to provide connections between the chip and the corresponding electronic package substrate, as is the case when using wire-bonding or TAB bonding techniques for connecting a chip to the electronic package substrate, the entire surface area of a chip can be used for creating electrical connections by providing electrically conductive terminals on one of the planar surfaces of the chip—denoted as the bottom surface of the chip. The electrical terminals on the bottom surface of the chip, which enable connections to the electronic package substrate, are typically arranged in an array covering most of the surface. Typically, small solder bumps are connected to the terminals on the chip to provide means for connecting the chip to the electronic package substrate. To connect a chip that has this array of solder bumps to a corresponding electronic package substrate, the chip is “flipped” onto the electronic package substrate, and the solder bumps are aligned with a corresponding array of solder bump pads on the electronic package substrate that has been designed and fabricated to accommodate the specific chip. Typically, the electronic package substrate with the solder bumps that are attached to the chip resting on the solder bump pads of the electronic package substrate is heated briefly to a temperature well above the melting temperature of the solder bumps causing the solder bumps to melt and to bond with the solder bump pads. Upon cooling the solder bumps provide mechanical and electrical connections between the electrical contacts or terminals of the chip and the electrical terminals or connections on the electronic package substrate. A chip that has electrically conductive bumps, such as solder bumps, for connecting the chip to an electronic package substrate is generally referred to as a flip chip. An electronic package substrate that is designed to accommodate a flip chip is called a flip chip package substrate.
Just as solder bumps are used to connect a flip chip to a flip chip package substrate, solder balls typically are used to connect a flip chip electronic package to the next level of integration, such as a printed circuit board (PC board or PCB). An electronic package that is designed to use an array of solder balls for making such connections to the next level of integration is called a ball grid array (BGA) electronic package. A BGA electronic package has an array of solder ball pads to which a corresponding array of solder balls is attached for connecting the BGA electronic package to a PC board. The solder ball grid array pattern is sometimes called the footprint of the electronic package. Most flip chip electronic packages use a BGA footprint and are often called BGA flip chip electronic packages. Some electronic packages employ pin connectors, instead of solder balls, for connecting to PC boards.
The term “solder bump” is generally applied to the solder connectors that connect a flip chip to an electronic package substrate, more particularly, to a flip chip package substrate. The term “solder ball” is generally applied to the solder connectors that are used to connect a BGA electronic package to a PC board. Solder bumps typically are about 100 microns or about 4 mils in diameter—much smaller than solder balls, which typically are about 1000 microns or about 40 mils.
As integrated circuits have become more dense, and as chip speeds have increased, over time, the amount of heat generated by chips during their operation also has increased, presenting additional demands upon the electronic package substrate to dissipate heat and to prevent the chip from becoming too hot to operate reliably. When the operating temperature of a chip rises above a certain high temperature range, the chip may become unreliable and fail or produce errors. The high temperature limits for safe and reliable operation of silicon chips today range from about 105° C. to about 115° C. To prevent chips, particularly those with high circuit densities and those that operate at high speeds, from over-heating and breaking down or becoming unreliable at high temperatures, it is essential that electronic packages conduct heat away from the chips and to dissipate the heat from the electronic package. Electronic packages that are designed to dissipate the heat generated in chips are commonly called thermally enhanced electronic packages. The thermal enhancement of the package is usually provided by attaching, to the package, a metallic structure that functions as a heat sink. An electronic package with a heat sink can draw heat out from the chip and then dissipate the heat to the surroundings by convection, conduction and/or radiation. In some electronic packages, the heat sink is added in a separate process step to improve thermal performance, whereas in others the heat sink is an integral part of the electronic package.
As currently made, a typical electronic package substrate for a thermally enhanced BGA wire bonded electronic package comprises (1) a support member and (2) a circuitized member. The support member typically is metallic and typically functions as a support and a heat sink for a chip and as a support or stiffener for the circuitized member. A typical circuitized member may be made from a polyimide substrate or from more rigid single or multilayered organic materials. Typically, the polyimide substrate is embedded with or covered by conductive traces, which may be photo-lithographically developed, providing for interconnecting the input and output terminals of a chip to the external terminals of the electronic package.
In some types of thermally enhanced electronic packages there is a cavity in the metallic support member into which a chip can be placed. Cavities in the metallic member are formed either by milling, etching, or stamping a cavity into the metal support member. The thermally enhanced BGA packages described in U.S. Pat. No. 5,376,588, U.S. Pat. No. 5,397,921, U.S. Pat. No. 5,728,606, and U.S. Pat. No. 5,409,865 show packages with cavities that have been etched out or milled out of the metallic substrate. Thermally enhanced BGA packages described in U.S. Pat. No. 5,663,530 and U.S. Pat. No. 5,773,884 show cavities that have been stamped into the metallic substrate. Generally the circuitized member is bonded to the metallic member by a thin layer of adhesive applied in a paste form.
The processes currently used to make a cavity in an electronic package substrate into which a chip can be placed are relatively expensive, can produce toxic waste, can introduce geometric distortions that tend to limit the speeds at which chips can operate, and often can lessen the structural integrity of the electronic package. Milling out a cavity in a metal support member is a relatively expensive operation. The high cost of the operation and the cost of the material wasted in the milling add significantly to the cost of the electronic package substrate.
Etching a cavity in a metal support member—a common process for making the cavity—is also an expensive operation, though less expensive than milling a cavity. Etching, however, not only wastes material, but it also produces toxic waste products, and it can produce thin spots and depressions in the base of the cavity, which may adversely affect the structural integrity of the electronic package substrate. Etching also creates geometric problems at the base of the cavity, such as rounded transitions from the side walls to the bottom wall or base—rather than a sharply defined and perpendicular intersection of the side walls and the bottom wall.
Another method of forming a cavity is by stamping a cavity into a metal piece, but stamping can weaken the metal and adversely affect the structural integrity of the electronic package substrate. Stamping also produces geometric problems in the base or bottom wall of the cavity, since stamping also produces rounded transitions from the side walls to the bottom wall of the cavity.
Rounded transitions from the side walls to the bottom wall are impediments to decreasing the distance between the chip and the electrical contacts on the electronic package substrate and adversely affect the electrical performance of the electronic package. Rounded transitions at the intersection of the side walls and the bottom wall of the cavity prevents a chip from being placed close to the side walls of the cavity. If a chip were placed too close to one or more of the side walls of a cavity formed by stamping or etching, the chip would be tipped by the rounded transitions where the side walls roll into the bottom wall of the cavity. Such a tipped chip not only would loose substantial mechanical and thermal contact with the heat sink, but it also would be askew and make it more difficult to form electrical connection, such as wire bonds or tabs, in an automatic bonding machine. Because the transitions from the side walls to the bottom wall or base of the cavity are rounded when the cavity is etched or stamped, it is necessary to make the cavity substantially larger than the dimensions of the chip to provide sufficient allowance or clearance for the rounded transitions from side walls to base. Since the chip will not be close to the side walls of the cavity, the wire bonds that connect the chip to wire bond pads on the circuitized member must be made longer than would be the case if the side walls and the base had a sharply defined, perpendicular intersection and the chip could be placed closely adjacent to the side walls of the cavity. In general, increasing the length of the wire bonds decreases the electrical performance of the electronic package. The shorter the wire length, the better it is for electrical signals. The usual methods (stamping or etching) for making the cavities, into which chips are placed produce an inherent impediment to decreasing the distance between the chip and the bonding pads on the electronic package substrate, thereby limiting the abilities of these electronic packages.
In etched cavities the length of the rounded bottom from the edge of the wall to the point where it becomes planar with the base of the cavity is, as a rule of thumb, half the depth of the etched cavity. For a typical etched cavity the depth may be approximately 450 microns, therefore the length of the rounded bottoms at the base of the etched copper stiffener is approximately 225 microns. The depth of the cavity is a sum of the thickness of the die attach, chip and height of wirebonds from the surface of the chip surface to the surface of the circuitized member. Because of the rounded bottom, the chip has to be placed at least 225 microns away from the edge of the cavity wall, otherwise the chip may tilt and thereby cause wire bonding and reliability issues. Placing the chip 225 microns from the wall of the copper stiffener causes an increase in the wire bond length by at least 225 microns. The average length of wire bonds range from 1000 microns to 2500 microns. A cavity in an electronic package substrate with perpendicular or squared transition between the side walls and the bottom wall rather than a rounded transition between the side walls and the bottom wall would result in a decrease in the length of the wirebond by approximately 225 microns. A decrease of 225 microns in the length of the wirebond, translates to about 9% to 22.5% of the current range of lengths of wirebonds and would result in a significant improvement in the electrical performance. Clearly there is a need for a better way to make wire bonded electronic package to produce cavities that do not have rounded transitions between side walls and bottom wall.
Faster microprocessors with higher power consumption and higher currents are not only generating additional heat that must be dissipated by the electronic package, but these microprocessors are generating more electromagnetic interference (“EMI”) that is becoming increasingly problematic for other components in other parts of the device. Faster microprocessors and other chips also can be vulnerable to EMI from external sources that interfere with the correct operation of the chip. In the past, the conventional way to deal with EMI was to build a bigger and better chassis enclosure; however, the apertures in the chassis required for airflow for cooling provide large windows for noise from high frequency signals and their harmonics to leak through. More recently designers have been designing and making metal enclosures, based upon the principles of a Faraday Cage, to surround electronic packages. These metallic structures, if properly designed, mounted, and grounded, appear to suppress or significantly reduce EMI generated by the microprocessor, and to suppress or significantly reduce the conduction of noise generated by other sources on a PC board to the microprocessor. These structures often are solid metal enclosures that are brazed together. Metal structures with metal screens or metal structures with small openings may reduce EMI adequately, so long as the small openings in the screen or other structure is smaller than the wavelength of the EMI. An electromagnetic wave with a frequency of 15 gigahertz has a wavelength of 2 cm. The 10× harmonic has a wavelength of 2 mm. A metal enclosure with some gaps no larger than 1–2 mm generally will provide protection against EMI from sources with frequencies up to 15 gigahertz. While these metallic structures have provided considerable benefits in reduction of EMI, the additional structure adds to the cost of the product and takes up additional space in the product. In some products, e.g. compact mobile phones, there may not be enough space for adding a Faraday Cage to the already crowded PC board. Hence there is a real need for both a wire bonded electronic package and a flip chip electronic package that incorporates its own Faraday Cage or the essential elements of a Faraday cage in the basic structure of the electronic package, so that EMI can be mitigated without the need for an additional metallic structure external to the electronic package. PC Boards often have and easily can be constructed with one or more ground planes as one of the layers within the PCB. Since the ground plane within a PCB directly under an electronic package can serve as the bottom side of a Faraday Cage, there is an opportunity and a need for an electronic package that incorporates its own grounded metallic structure around the top and four sides of a chip so that the electronic package can be placed above a ground plane in a PC board and shield the chip from and against EMI.
With the increasing size and complexity of chips there is a corresponding increase in the number of inputs and outputs (I/Os) of chips. As the size of chips and devices shrinks, there is a need to make more connections and denser connections in the electronic package substrate. There is also a need to reduce the number of discrete, individual paths between the chip and the PC board. To reduce the number of paths and to accommodate an increase in the number of I/Os for a chip without increasing the number of solder balls in an array of solder balls it has become a common practice to use a two-side circuitized member and to incorporate a ground plane into one side or a part of one side of the circuitized member. Alternatively a multilayered circuitized member can be used, but using multilayer circuitized members significantly increases the cost of an electronic package. Since thermally enhanced electronic package generally have a metal heat sink, it would be desirable to find a cost effective way to use the metal heat sink as a ground plane and to make connections thereto efficiently so that valuable space on the circuitized member that otherwise would be used for a ground plane or for traces routing ground signals to the ground plane can be freed up to handle more signals or a power plane.
As demands to improve the heat dissipation properties and electrical performance of electronic packages have increased, there has been a tendency to add components to the electronic package and to make packages more elaborate and complex. Unfortunately, as electronic packages have become more elaborate and complex, there are now more components and more interfaces and interconnections that can fail. As a general rule, the overall reliability of any product or system, including an electronic package, can be improved by reducing the number of components and the number of connections in the product or system that can fail. There is a need for an electronic package substrate and an electronic package that can provide the requisite increased heat dissipation, and improved electrical performance with fewer components.
Flip chip electronic packages share with wire bonded electronic packages the limitations, problems and needs for solutions relating to EMI, the need to improve the efficiency of routing electrical connections, and the need to provide heat dissipation in a cost effective and component-minimizing manner. Flip chip electronic packages also are subject to problems peculiar to the way that flip chips are attached to flip chip package substrate that are not pertinent to wire bonded electronic packages.
The process of attaching BGA electronic packages to PC boards requires that solder balls on the BGA electronic package melt and bond with solder ball pads on the PC Board. The process for attaching an electronic package to a PC board is referred to as the package-to-board assembly process. Typically, solder balls on electronic packages are made of eutectic (about 63% Sn, 37% Pb) or near eutectic (about 60% Sn, 40% Pb) lead tin solder that melts about 183.6° C. During the package-to-board assembly process the temperature of the electronic package and the temperature of the PC board are raised significantly above 183.6° C. to compensate for heat absorption and dissipation by various components on the PC board, to enable the kinetics of solder melting in a short period of time, and to ensure that the solder balls melt and attach to the solder ball pads on the PC board. In a typical package-to-board assembly process, the PC board, with the electronic package set in proper position (i.e. with the array of solder balls on the electronic package aligned with the array of solder ball pads on the PC board), is sent through an oven exposing the PC board to a temperature that rises at the rate of about 3° C./second until the temperature reaches about 150° C.; the temperature generally is held at about 150° C. for a minimum of about 60 seconds to a maximum of about 120 seconds; the temperature then is raised at the rate of about 2.5° C./second until the temperature reaches about 235° C.; the temperature generally is held at about 235° C. for a minimum of about 15 seconds to a maximum of about 20 seconds, during which the soldering is effected; the temperature is then lowered during the cooling phase at a rate of about 3° C./second.
Most PC boards are made of organic materials, such as a material commonly known in the industry as FR-4 (sometimes written as FR4) or a similar material known as BT resin (or just BT), a resin supplied by Mitsubishi Corporation of Japan. (The acronym FR is short for fire resistant.) Electronic package substrates for many, if not most, BGA flip chip electronic packages are made of the same organic materials—FR-4 or BT resin. These organic materials have a glass transition temperature of about 150° C. to about 170° C., a temperature above which the materials begin to soften, and a breakdown temperature of about 225° C. to about 235° C., a temperature above which the materials can char or begin to burn. These organic materials will be damaged if exposed to temperatures above 225° C.–235° C. for a sustained time period. In a typical package-to-board assembly process, the temperature of the PC board is raised to about 225° C.–235° C. for a short period of time, to quickly melt the solder balls, and then is quickly lowered, to prevent damage to the PC board and the electronic package substrate material.
High temperatures applied to organic materials, like FR-4 or BT resin, particularly if sustained for a significant period of time, can cause a number of problems that manifest themselves after the electronic package is put into service. Higher temperatures will cause or lead to increased warping of the electronic package, which can adversely affect the integrity of the electronic package and its connections to a PC board. Higher temperatures also lead to an increase in the formation of intermetallics between the solder in the solder balls and the metal layers of the solder ball pads, which cause brittleness in the bonds between the solder balls and the solder ball pads. The encapsulating material used to seal and protect the chip and its connections in an electronic package typically is an organic material. This material absorbs moisture. This moisture turns to steam during the reflow process. If the temperature is too high, or if the electronic package is held at a high temperature too long, the steam cracks the electronic package. This phenomenon has been observed widely and is called “popcorning.” Electronic packages that are exposed to higher maximum temperature during the solder reflow process or that are exposed to the maximum temperature for a longer period of time are more susceptible to popcorning. Cracks that are formed in the encapsulating material as a result of popcorning allow moisture or other chemicals to penetrate the electronic package, causing a reliability problem. To avoid these problems, it is important—often critical—to keep the maximum temperature during the package-to-board assembly process as low as possible and to maintain the high temperature for as short a time as possible.
Typically, the solder connections between a flip chip and a flip chip package substrate are encapsulated with an epoxy compound, commonly referred to as an “underfill” in the industry. The solder bumps are encapsulated after the flip chip is soldered onto the flip chip package substrate. The underfill encapsulation binds the chip, the flip chip package substrate, and the solder bumps together and strengthens the mechanical bonding between the chip and the solder bumps and the mechanical bonding between the solder bumps and the flip chip package substrate. The underfill encapsulation increases the reliability and lifetimes of the flip chip-to-solder bump interconnections and the reliability and lifetimes of the solder bump-to-flip chip substrate interconnections.
If the solder bumps melt a second time during the package-to-board assembly process, the volume of the solder bumps will increase during the phase change from solid to liquid. The volume of the solder bumps subsequently will decrease during the cooling cycle as the solder undergoes a second phase change from liquid to solid. The increase in volume of the solder bumps during the phase change from solid to liquid puts pressure on the epoxy underfill encapsulant causing interfacial separation in the interface between the underfill encapsulant and the chip and in the interface between the underfill encapsulant and the solder bump. The subsequent decrease in volume of the solder bumps during the phase change from liquid to solid will leave a gap where there has been an interfacial separation. The interfacial separation results in a loss of mechanical bonding between the flip chip and the flip chip package substrate, thereby degrading the mechanical reliability of the solder bump connections. Gaps at the points of interfacial separation degrade the electrical reliability of the solder bump connections.
To maintain the reliability of the electrical and mechanical connections of the solder bumps (or other electrically conductive bumps) between the flip chip and the flip chip package substrate, it is critical to ensure that the solder bumps (or other electrically conductive bumps) connecting the flip chip to the flip chip package substrate do not melt during the package-to-board assembly process. One way to ensure that the solder bumps on the flip chip do not melt during the package-to-board assembly process is to select a material for the solder bumps that has a melting temperature that is greater than the maximum temperature of the package-to-board assembly process, usually 225° C.–235° C. Typically, solder bumps on flip chips are composed of high lead solder (90% Pb, 10% Sn) that melts around 300° C. Other alloy compositions of lead and tin and alloy compositions other than lead and tin are alternatives for making solder bumps. But, regardless of the alloy chemistry and composition, the solder bumps connecting the flip chip to the flip chip package substrate should have a melting temperature that is substantially higher than the temperature at which the solder balls are melted in connecting the electronic package to the PC board during the package-to-board assembly process.
Because the melting temperature of the solder bumps (or other electrically conductive bumps) on flip chips typically is substantially greater than 225° C.–235° C., the temperature required to melt and attach the solder bumps on the flip chip to the flip chip package substrate in a conventional reflow oven generally is raised substantially higher than 225° C.–235° C. Therefore, the materials used to make the flip chip package substrate should be able to withstand temperatures that are substantially higher than 225° C.–235° C. This requirement has heretofore limited the choice of materials that can be used for the flip chip package substrates.
Flip chip package substrates made of ceramic material are generally used for flip chips that have solder bumps that melt at temperatures greater than 225° C. Electronic package substrates made of ceramic are generally more expensive than electronic package substrates made of organic material.
To get around the problem of not being able to use high-melting-temperature solders with organic electronic package substrates, novel methods have been developed to apply a ‘cap’ of low melting eutectic solder on high lead solders bumps. These methods are described in U.S. Pat. No. 6,127,735 to Berger, et al., entitled “Interconnect for low temperature chip attachment” and U.S. Pat. No. 5,451,274 to Gupta, entitled “Reflow of multi-layer metal bumps.” However, because of competitive pressures on the manufacturing of electronic packages, there is a need for a lower cost solution to the problem.
There is an increasing recognition of the hazzards associated with lead in the environment. Proposed legislative action, pressure by the environmental activists, and a sense of community responsibility are prompting manufacturers to reduce—and ultimately to eliminate if possible—the use of lead in electronic products. There are a number of alloy chemistries being evaluated to replace traditional Lead/Tin solder alloys. The most promising being investigated are ternary alloys of Tin(Sn), Silver(Ag), and Copper(Cu). The alloy compositions of these ternary alloys being evaluated are 95.5% Sn/4.0% Ag/0.5% Cu and 95.5% Sn/3.8% Ag/0.7% Cu. The melting temperature of both of these alloys is about 217° C., which is greater than the melting temperature of eutectic Pb/Sn solder, 183.6° C.
If solder bumps made of 95.5% Sn/4.0% Ag/0.5% Cu and 95.5% Sn/3.8% Ag/0.7% Cu are used, the temperature required in a conventional solder reflow oven that is used in the chip-to-substrate attachment process to melt the solder bumps will need to be in the range of about 240° C.–250° C. The higher temperature required to melt the solder bumps in the typical chip-to-substrate attachment process will limit the type of materials that can be used for making the flip chip package substrate and may preclude the use of low-cost organic material in making flip chip package substrates.
Since organic materials are significantly less expensive than ceramic materials, and since organic materials have other advantages over ceramic materials in an electronic package substrate, it is desirable to make flip chip electronic package from organic materials. Hence there has been and is a real need for a reliable process—different from the conventional process of using a reflow oven-for attaching flip chips with solder bumps that have high melting temperatures (in the range of about 215° C.–250° C. or higher) to flip chip substrates made of commonly used and relatively inexpensive organic materials, without damaging the substrates.
To facilitate handling in automated assembly machines that can perform operations on multiple electronic packages simultaneously, it is a common practice to join multiple electronic package substrates in a row or in a matrix or array. Typically four to six electronic package substrates are joined together by what is commonly referred to as a lead frame. For example, in making multiple thermally enhanced BGA wire bonded electronic packages, such as Tape Ball Grid Array (sometimes called by the acronym “TBGA”) packages, the metal body that is used as a support member and as a heat sink often is extended to join several electronic package substrates in a row so that typically four to six electronic packages can be made simultaneously. After the multiple electronic packages are assembled, it is necessary to singulate the packages, by either sawing or stamping out the individual electronic packages. Because of the continuing need to reduce costs in the electronic package industry, it would be highly desirable to develop a frame for making multiple electronic packages that can be made of a lower cost material and that can reduce the time for fabricating multiple electronic packages and reduce the time for singulating electronic packages from the frame. This need is felt in fabricating, assembling, and singulating wire bonded electronic package and in fabricating, assembling, and singulating flip chip electronic packages.
In summary, in the electronics industry, there is a constant demand to increase the electrical performance of integrated circuits and correspondingly the electrical performance of electronic packages. There also is a constant demand to increase the reliability of an electronic package during its useful life. There also is a constant demand to decrease the cost of electronic components, including electronic packages. It should be apparent from the foregoing that there is a need for a wire bonded electronic package that can be made from fewer components than are required for current wire bonded electronic packages and that can be made with fewer and simpler process steps than are required to make current wire bonded electronic packages and that can be made at a lower cost and that can achieve high reliability and superior electrical performance. It also should be apparent from the foregoing that there is a need for a flip chip electronic package that can be made from fewer components than are required for current flip chip electronic packages, that can be made of relatively inexpensive organic materials and yet be able to accommodate and incorporate a flip chip with Pb/Sn solder bumps or solder bumps made of other alloys that melt at temperatures greater than 250° C., that can be made with fewer and briefer process steps than are required to make current flip chip electronic packages, that can be made at a lower cost than current flip chip electronic packages, and that can achieve high reliability and superior electrical performance. It also should be apparent from the foregoing that there also is a need to for electronic packages for both wire bonded chips and flip chips that incorporate means for protecting the chips against EMI and for suppressing EMI generated by the chips. It also should be apparent from the foregoing that there also is a need for electronic packages for both wire bonded chips and flip chips that incorporate means for more efficient routing and use of space to accommodate the ever increasing demand for higher density routing.